V-Tec C5-AT25/D4 Instrukcja Użytkownika Pobierz pdf (Strona 16)

MAX8520/MAX8521

6) To ensure high DC loop gain and minimum loop

error, keep the board layout adjacent to the negative

input pin of the integrator (U2 in Figure1) clean and

free of moisture. Any contamination or leakage

current into this node can act to lower the DC gain of

the integrator, which can degrade the accuracy of

the thermal loop. If space is available, it can also be

helpful to surround the negative input node of the

integrator with a grounded guard ring.

Refer to the MAX8520/MAX8521 evaluation kit for a PC

board layout example.

Chip Information

TRANSISTOR COUNT: 3007

PROCESS: BiCMOS

Smallest TEC Power Drivers for

Optical Modules

16 ______________________________________________________________________________________

OS1

OS2

16 PV

FREQ

PGND2

LX2

GND

COMP

SHDN

PGND1

LX1

5ITEC

MAXIN

MAXIP

MAXV

REF

10CTLI

MAX8520/

MAX8521

TOP VIEW

THIN QFN

LX2 LX2 N.C. N.C. LX1 LX1

PGND2 PGND2 PGND2 PGND1 PGND1 PGND1

OS2 FREQ GND2 GND2 COMP

SHDN

VDD GND2 N.C. N.C. GND2 ITEC

GND CTLI REF MAXV MAXIP MAXIN

2 CS OS1 PV

1PV

F5 F4 F3 F2 F1

E6 E5 E4 E3 E2 E1

D6 D5 D4 D3 D2 D1

C6 C5 C4 C3 C2 C1

B6 B5 B4 B3 B2 B1

A6 A5 A4 A3 A2 A1

UCSP

MAX8521

Pin Configurations

1 2 ... 11 12 13 14 15 16 17 18 19

MAX8520/MAX8521 1
Optical Modules 1

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